Platform Delivers Superior Verification Efficiency for Mixed-Signal and RF Analysis
SANTA CLARA, CA, —May 19, 2009— Berkeley Design Automation Inc., provider of the Analog FastSPICE™ unified circuit verification platform for advanced analog and RF integrated circuits (ICs), today announced that Panasonic Corporation, a world leader in products, systems, and components for consumer electronics, has selected the company's Analog FastSPICE™ platform for use in their production flow for verification of mixed-signal integrated circuits.
"We spend a significant amount of effort on mixed-signal verification and noise analysis of mixed-signal integrated circuits," said Masahiko Matsumoto, Director of the Analogue LSI Business Unit, Semiconductor Company, Panasonic Corporation. "After a rigorous evaluation of the Analog FastSPICE platform on a variety of mixed-signal integrated circuits, we have decided to deploy this platform for mass-production use in Panasonic."
Analog FastSPICE is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. Always delivering true SPICE accurate results, it provides 5x-10x higher performance than traditional SPICE, >1 million-element capacity, and the industry’s only comprehensive noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. AFS Platform tools include: AFS Nano SPICE simulator, Analog FastSPICE circuit simulator, Noise Analysis Option™ device noise analyzer, and RF FastSPICE™ multi-tone periodic analyzer.
"Today, we are seeing leading companies all over the world embarking on a major retooling for next-generation analog, mixed-signal, and RF design to improve their verification efficiency," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We are delighted that Panasonic Corporation has chosen to deploy the Analog FastSPICE platform for production use. This adoption validates, once again, that Berkeley Design Automation is an essential partner as companies embark on new tooling strategies for greater verification efficiency."
About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog, mixed-signal, and RF (AMS/RF) verification. Its Analog FastSPICE unified circuit verification platform combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Design teams from top-10 semiconductor companies to leading startups use the AFS Platform to efficiently verify AMS/RF circuits. Founded in 2003, the company has received several industry awards in recognition of its technology leadership and impact on the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corporation, and NTT Corporation For more information, see http://www.berkeley-da.com.
Tuesday, May 19, 2009
Monday, January 12, 2009
IPextreme to Give Tutorial on Industry’s First IP-based Design Methodology at DesignCon 2009
SILICON VALLEY, California – January 9, 2009 – At DesignCon 2009 in Santa Clara, CA from February 2-5, 2009, IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, is giving a CoReUse™ tutorial; featuring licensable, technology-independent Power Architecture processors in the Power.Org booth; and exhibiting. .
Tutorial:
What: “CoReUse/ QCore – Industry’s First IP-based Design Methodology and IP Compliance-checking Tool,” will give attendees a good understanding of the CoReUse IP-based design methodology and QCore CoReUse Compliance tool. Developed and used at NXP Semiconductors over the last 10 years, CoReUse represents not only the industry’s leading example of IP reuse at work, but is a living and practical IP-based design methodology that can adapt to changing technologies, standards, and EDA flows and that provides a proven framework for companies to develop and use semiconductor intellectual property. Since maintaining compliance to any methodology is difficult, NXP also developed QCore, a tool that is used for checking an IP’s compliance with the CoReUse standard.
Each attendee will receive one free printed copy of the CoReUse manual.
Track: TF-MP1
http://www.designcon.com/2009/attendees/schedule/1_tf_mp_1.asp
Who: Taught by Pierre Thomas, Vice President, Engineering, IPextreme, Inc.
When: Monday, February 2nd, from 1:30 to 4:30 pm
Registration: To register, please go to -- http://www.designcon.com/2009/register/
Power.org Exhibit Booth
IPextreme has been a member Power.org since 2006 and will be present, along with other members of the Power.org ecosystem, at the Power.org booth on February 3-4th. IPextreme and other members of Power.org will be presenting overviews of their respective Power Architecture solutions on February 5th.
What: IPextreme will be featuring its portfolio of licensable, synthesizable, technology-independent Power Architecture microprocessors
Who: Warren Savage, President and CEO, IPextreme, Inc. and Rick Tomihiro, Vice President, Marketing, IPextreme, Inc.
When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST
Where: Power.org Booth #753 (exhibition floor on Feb 3-4th) and Power.org Room #212 (on
February 5th. Times will be announced at the show.)
IPextreme Exhibit Booth
What: IPextreme provides designers with famous IP from leading semiconductor companies and has an extensive portfolio of automotive, consumer and processor IP. IPextreme will be available to answer questions in their booth on CoReUse, QCore or any of their available IP cores. There will also be a drawing twice daily to win a yearly subscription to the CoReUse Foundation eBooks.
When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST
Where: Booth #841
All events will be held at DesignCon (http://www.designcon.com/2009/) in the Santa Clara Convention Center, 5101 Great America Parkway, Santa Clara, California.
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc. All other product or service names are the property of their respective owners. All rights reserved.
Tutorial:
What: “CoReUse/ QCore – Industry’s First IP-based Design Methodology and IP Compliance-checking Tool,” will give attendees a good understanding of the CoReUse IP-based design methodology and QCore CoReUse Compliance tool. Developed and used at NXP Semiconductors over the last 10 years, CoReUse represents not only the industry’s leading example of IP reuse at work, but is a living and practical IP-based design methodology that can adapt to changing technologies, standards, and EDA flows and that provides a proven framework for companies to develop and use semiconductor intellectual property. Since maintaining compliance to any methodology is difficult, NXP also developed QCore, a tool that is used for checking an IP’s compliance with the CoReUse standard.
Each attendee will receive one free printed copy of the CoReUse manual.
Track: TF-MP1
http://www.designcon.com/2009/attendees/schedule/1_tf_mp_1.asp
Who: Taught by Pierre Thomas, Vice President, Engineering, IPextreme, Inc.
When: Monday, February 2nd, from 1:30 to 4:30 pm
Registration: To register, please go to -- http://www.designcon.com/2009/register/
Power.org Exhibit Booth
IPextreme has been a member Power.org since 2006 and will be present, along with other members of the Power.org ecosystem, at the Power.org booth on February 3-4th. IPextreme and other members of Power.org will be presenting overviews of their respective Power Architecture solutions on February 5th.
What: IPextreme will be featuring its portfolio of licensable, synthesizable, technology-independent Power Architecture microprocessors
Who: Warren Savage, President and CEO, IPextreme, Inc. and Rick Tomihiro, Vice President, Marketing, IPextreme, Inc.
When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST
Where: Power.org Booth #753 (exhibition floor on Feb 3-4th) and Power.org Room #212 (on
February 5th. Times will be announced at the show.)
IPextreme Exhibit Booth
What: IPextreme provides designers with famous IP from leading semiconductor companies and has an extensive portfolio of automotive, consumer and processor IP. IPextreme will be available to answer questions in their booth on CoReUse, QCore or any of their available IP cores. There will also be a drawing twice daily to win a yearly subscription to the CoReUse Foundation eBooks.
When: Tuesday & Wednesday, February 3rd & 4th, 2009 from 12:30 to 6:30 pm PST
Where: Booth #841
All events will be held at DesignCon (http://www.designcon.com/2009/) in the Santa Clara Convention Center, 5101 Great America Parkway, Santa Clara, California.
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc. All other product or service names are the property of their respective owners. All rights reserved.
Apache Design Solutions Introduces RedHawk-NX, the Next Generation Full-chip Dynamic Power Integrity Solution
The industry’s first “hierarchical dynamic” solution delivers capacity and performance required for the most advanced technology designs
San Jose, Calif. – January 7, 2009 – Apache Design Solutions, the technology leader in power and noise analyses and signoff for chip, package, and system designs, today announced RedHawk-NX, the next generation dynamic power integrity solution re-architected to handle designs of five hundred million gates. The advanced technologies in RedHawk-NX include the industry’s first hierarchical dynamic power analysis, proprietary mesh pattern recognition and reuse, and multi-core support, enabling designers to analyze the most complex designs with sign-off accuracy.
As the semiconductor companies continue to push the capacity and performance limitations of EDA tools, Apache’s ability to deliver products that meet their demands provides key competitive advantage. Apache’s continuous investment in R&D has enabled the company to deliver re-architected next generation dynamic power solutions every three years, starting with the introduction of RedHawk-SD in 2002, RedHawk-EV in 2005, and RedHawk-NX in 2008. Each generation of products offers higher capacity and performance to address the latest design complexity in CPU, GPU, NPU, and devices with large memory contents.
“RedHawk technology roadmap is able to meet our design size and complexity needs for power noise analysis from one generation of our products to the next,” said Jean Boufarhat, vice president of engineering, from Graphics Products Group at AMD. “Specifically, RedHawk-NX allowed us to perform dynamic power noise analysis on our largest design with more than 750 million nodes. The ability to verify the entire chip including memories is critical to our design success.”
Hierarchical Dynamic (HD)
RedHawk-NX supports the industry’s first hierarchical dynamic technology allowing designers to adopt a bottom-up analysis methodology with various levels of abstraction. When using HD’s ‘white-box’ mode, the designers are able to maintain the same level of sign-off accuracy as RedHawk’s flattened analysis. By using HD’s ‘gray-box’ mode, designers gain additional capacity improvement.
Historically, hierarchical solutions were only available for static analysis where time-point-by-time-point waveform accuracy of the block-level simulation is not considered. With HD technology, IP providers can deliver encrypted Apache dynamic power views for use in full-chip sign-off analysis. HD also effectively supports industry’s hierarchical design methodologies across multiple design sites.
Mesh Pattern Recognition (MPR)
RedHawk-NX’s automatic mesh pattern recognition algorithm leverages regularity in the power/ground mesh structures enabling data reuse for effective reduction of physical memory needs. MPR handles designs with complex RDL, dense multi-layered P/G grid, and high memory content. MPR technology has been demonstrated to reduce RedHawk database memory footprint by 2-3X compared with existing techniques.
Multi-core Architecture (MC)
RedHawk-NX is re-architected to maximize the capacity and performance advantages of the multi-core processing systems. The MC solver can be scaled to handle designs with up to billion nodes in existing computing environment. With the MC technology, designers will benefit from 2-3X runtime improvements in their dynamic transient simulation, as well as MTCMOS rush current analysis.
“SoC power integrity and power induced system noise are clearly the top challenges for the semiconductor industry,” said Andrew Yang, CEO of Apache. “Power and noise is Apache’s focus and we continuously invest in R&D to maintain our ‘best-in-class’ and ‘first-in-class’ leadership position. This enables us to address customers growing design challenges and cost reduction needs.”
Apache Design Solutions, CPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc
San Jose, Calif. – January 7, 2009 – Apache Design Solutions, the technology leader in power and noise analyses and signoff for chip, package, and system designs, today announced RedHawk-NX, the next generation dynamic power integrity solution re-architected to handle designs of five hundred million gates. The advanced technologies in RedHawk-NX include the industry’s first hierarchical dynamic power analysis, proprietary mesh pattern recognition and reuse, and multi-core support, enabling designers to analyze the most complex designs with sign-off accuracy.
As the semiconductor companies continue to push the capacity and performance limitations of EDA tools, Apache’s ability to deliver products that meet their demands provides key competitive advantage. Apache’s continuous investment in R&D has enabled the company to deliver re-architected next generation dynamic power solutions every three years, starting with the introduction of RedHawk-SD in 2002, RedHawk-EV in 2005, and RedHawk-NX in 2008. Each generation of products offers higher capacity and performance to address the latest design complexity in CPU, GPU, NPU, and devices with large memory contents.
“RedHawk technology roadmap is able to meet our design size and complexity needs for power noise analysis from one generation of our products to the next,” said Jean Boufarhat, vice president of engineering, from Graphics Products Group at AMD. “Specifically, RedHawk-NX allowed us to perform dynamic power noise analysis on our largest design with more than 750 million nodes. The ability to verify the entire chip including memories is critical to our design success.”
Hierarchical Dynamic (HD)
RedHawk-NX supports the industry’s first hierarchical dynamic technology allowing designers to adopt a bottom-up analysis methodology with various levels of abstraction. When using HD’s ‘white-box’ mode, the designers are able to maintain the same level of sign-off accuracy as RedHawk’s flattened analysis. By using HD’s ‘gray-box’ mode, designers gain additional capacity improvement.
Historically, hierarchical solutions were only available for static analysis where time-point-by-time-point waveform accuracy of the block-level simulation is not considered. With HD technology, IP providers can deliver encrypted Apache dynamic power views for use in full-chip sign-off analysis. HD also effectively supports industry’s hierarchical design methodologies across multiple design sites.
Mesh Pattern Recognition (MPR)
RedHawk-NX’s automatic mesh pattern recognition algorithm leverages regularity in the power/ground mesh structures enabling data reuse for effective reduction of physical memory needs. MPR handles designs with complex RDL, dense multi-layered P/G grid, and high memory content. MPR technology has been demonstrated to reduce RedHawk database memory footprint by 2-3X compared with existing techniques.
Multi-core Architecture (MC)
RedHawk-NX is re-architected to maximize the capacity and performance advantages of the multi-core processing systems. The MC solver can be scaled to handle designs with up to billion nodes in existing computing environment. With the MC technology, designers will benefit from 2-3X runtime improvements in their dynamic transient simulation, as well as MTCMOS rush current analysis.
“SoC power integrity and power induced system noise are clearly the top challenges for the semiconductor industry,” said Andrew Yang, CEO of Apache. “Power and noise is Apache’s focus and we continuously invest in R&D to maintain our ‘best-in-class’ and ‘first-in-class’ leadership position. This enables us to address customers growing design challenges and cost reduction needs.”
Apache Design Solutions, CPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc
Thursday, December 18, 2008
IP Cores from IPextreme Support Mentor Graphics’ Precision® Synthesis FPGA Tool
IP cores now validated for Precision logic and physical synthesis flow
Silicon Valley, CA, California – December 19, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, has validated its Multi-CAN Controller, its CJTAG-IEEE1149.7 IP cores and its 32-bit Power Architecture e200, V1 ColdFire, V2 ColdFire, 16-bit CR16CP and 8-bit HCS08 processor cores for use with Mentor Graphics Precision® Synthesis flow. Designers can now use the advanced features of Precision Synthesis to quickly and easily achieve superior results when integrating IPextreme cores into FPGAs.
“IPextreme has a large catalog of silicon-proven, synthesizable FPGA cores,” said Daniel Platzker, product line director of FPGA synthesis at Mentor Graphics. “Mentor delivers a comprehensive, vendor-independent FPGA design flow, and compatibility between Precision Synthesis and the IPextreme cores ensures success for mutual customers.”
“We work closely with Mentor to confirm the compatibility of our IP with their EDA tools,” said Rick Tomihiro, vice president of marketing for IPextreme. “Not only is our IP validated on the Precision Synthesis tool, but also our XPack IP packaging, distribution, configuration and support technology automatically generates configuration and constraints files for Precision Synthesis, which delivers excellent results for FPGA designers.”
All validated cores are available today, through the IPextreme Core Store® (http://www.ip-extreme.com/corestore/) or by contacting the company at www.ip-extreme.com.
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
# # #
Contacts for IPextreme:
Karen Crannell, IPextreme Inc., 408-540-0096, Karen.Crannell@ip-extreme.com
Europe:
Annette Bley, Bley PR, +44 (0) 20 7482 4800, annette@annettebleypr.com
North America:
Linda Marchant , Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com
Silicon Valley, CA, California – December 19, 2008 – IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, has validated its Multi-CAN Controller, its CJTAG-IEEE1149.7 IP cores and its 32-bit Power Architecture e200, V1 ColdFire, V2 ColdFire, 16-bit CR16CP and 8-bit HCS08 processor cores for use with Mentor Graphics Precision® Synthesis flow. Designers can now use the advanced features of Precision Synthesis to quickly and easily achieve superior results when integrating IPextreme cores into FPGAs.
“IPextreme has a large catalog of silicon-proven, synthesizable FPGA cores,” said Daniel Platzker, product line director of FPGA synthesis at Mentor Graphics. “Mentor delivers a comprehensive, vendor-independent FPGA design flow, and compatibility between Precision Synthesis and the IPextreme cores ensures success for mutual customers.”
“We work closely with Mentor to confirm the compatibility of our IP with their EDA tools,” said Rick Tomihiro, vice president of marketing for IPextreme. “Not only is our IP validated on the Precision Synthesis tool, but also our XPack IP packaging, distribution, configuration and support technology automatically generates configuration and constraints files for Precision Synthesis, which delivers excellent results for FPGA designers.”
All validated cores are available today, through the IPextreme Core Store® (http://www.ip-extreme.com/corestore/) or by contacting the company at www.ip-extreme.com.
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
# # #
Contacts for IPextreme:
Karen Crannell, IPextreme Inc., 408-540-0096, Karen.Crannell@ip-extreme.com
Europe:
Annette Bley, Bley PR, +44 (0) 20 7482 4800, annette@annettebleypr.com
North America:
Linda Marchant , Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com
Wednesday, December 17, 2008
TSMC Selects Berkeley Design Automation Analog FastSPICE™ for Analog and Mixed-Signal IP Verification
Tool Delivers SPICE Accuracy Five to Ten Times Faster for Complex Analog/Mixed-Signal Circuits
SANTA CLARA, Calif.--(BUSINESS WIRE)--Berkeley Design Automation Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), today announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has selected the company's Analog FastSPICE™ circuit simulator for complex-block characterization and full-circuit performance simulation of its analog and mixed-signal design environment. TSMC selected Analog FastSPICE based on the tool’s SPICE accuracy and performance.
“TSMC provides the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows,” said ST Juang, Senior Director of TSMC’s Design Infrastructure Marketing Division. “We selected Analog FastSPICE for our design teams because it delivered SPICE accurate results five to ten times faster than traditional SPICE on our analog/mixed-signal IP and building blocks across our major process technologies down to 45nm.”
Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. By using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any accuracy compromising shortcuts. Design teams from top-10 semiconductor companies and leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems.
"We are delighted that TSMC selected Analog FastSPICE for their analog and mixed-signal design environment," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We see TSMC’s adoption of our products for their design teams as a testimonial to our Precision Circuit Analysis technology. We are proud to help TSMC's Design Service Division accelerate their analog/mixed-signal design verification."
About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine's 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see http://www.berkeley-da.com.
Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Contacts
PR for Berkeley Design Automation
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
michelle.clancy@cayennecom.com
SANTA CLARA, Calif.--(BUSINESS WIRE)--Berkeley Design Automation Inc., provider of Precision Circuit Analysis™ technology for advanced analog and RF integrated circuits (ICs), today announced that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has selected the company's Analog FastSPICE™ circuit simulator for complex-block characterization and full-circuit performance simulation of its analog and mixed-signal design environment. TSMC selected Analog FastSPICE based on the tool’s SPICE accuracy and performance.
“TSMC provides the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows,” said ST Juang, Senior Director of TSMC’s Design Infrastructure Marketing Division. “We selected Analog FastSPICE for our design teams because it delivered SPICE accurate results five to ten times faster than traditional SPICE on our analog/mixed-signal IP and building blocks across our major process technologies down to 45nm.”
Berkeley Design Automation tools include Analog FastSPICE™ circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE™ periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. By using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any accuracy compromising shortcuts. Design teams from top-10 semiconductor companies and leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems.
"We are delighted that TSMC selected Analog FastSPICE for their analog and mixed-signal design environment," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "We see TSMC’s adoption of our products for their design teams as a testimonial to our Precision Circuit Analysis technology. We are proud to help TSMC's Design Service Division accelerate their analog/mixed-signal design verification."
About Berkeley Design Automation
Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine's 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see http://www.berkeley-da.com.
Analog FastSPICE, Noise Analysis Option, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Contacts
PR for Berkeley Design Automation
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
michelle.clancy@cayennecom.com
Wednesday, December 10, 2008
IPextreme® Announces Availability of Freescale HCS08 Microprocessor IP Core
Synthesizable IP core available through IPextreme’s online Core Store™ for $10,000 licensing fee
SILICON VALLEY, Calif.--IPextreme, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, is adding the Freescale HCS08 8-bit microprocessor to its line of industry standard 16-bit and 32-bit microprocessors. The Freescale HCS08 is a synthesizable, state-of-the-art, high performance and low power 8-bit microprocessor that can be easily integrated into any ASIC or FPGA design. The HCS08 also provides an easy migration path to Freescale’s 32-bit ColdFire architecture. Using Freescale’s CodeWarrior integrated development environment, assembly code for the HCS08 can be retargeted to the 32-bit V1 ColdFire with just a few mouse clicks.
“We are pleased to continue to expand the portfolio of Freescale IP made available for licensing through IPextreme,” says Jeff Bock, Freescale’s Global Microcontroller Marketing Manager. “The HCS08 provides a low-cost entry point and an easy migration to our ColdFire Architecture, giving designers the flexibility they need. IPextreme’s Core Store™ enables designers to get through the IP purchase process quickly and allows them to focus on their designs.”
Freescale has shipped hundreds of millions of devices based on the HCS08 processor architecture and thousands of embedded systems are utilizing it. Since the HCS08 IP core is object code compatible with currently available Freescale 68HC08 and HCS08 devices, embedded systems currently based on these processors are easily migrated to ASICs or FPGAs, and all software is fully binary compatible. In addition, users of the HCS08 can leverage the immense ecosystem of evaluation systems, development systems, compilers and application software.
“The HCS08 is a microprocessor that has already been utilized in many market segments such as consumer, industrial, medical, automotive and low-cost networking. Providing embedded system designers with a synthesizable version allows them to integrate their designs into ASIC or FPGAs while leveraging the extensive ecosystem of hardware and software development tools and maintaining complete software compatibility,” said Rick Tomihiro, vice president of marketing for IPextreme. “As usual, IPextreme will package, license and support these synthesizable cores.”
Pricing and Availability
The Freescale HCS08 core is available for licensing now. Like all IPextreme IP, the core is offered in a complete package that includes synthesizable source code, integration test bench, and complete documentation. Encrypted versions of the core are available from the Core Store at US $10,000. Full source code versions of the HCS08 and other Core Store IP are also available for additional fees.
For additional product information, please see http://www.ip-extreme.com/IP/hcs08
To purchase the HCS08 please visit the Core Store at http://www.ip-extreme.com/corestore/
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
Contacts
IPextreme Inc.Karen Crannell, 408-540-0096Karen.Crannell@ip-extreme.comor
Europe: ley PRAnnette Bley, +44 (0) 20 7482 4800annette@annettebleypr.com
North America: Cayenne Communications Linda Marchant, 919-451-0776linda.marchant@cayennecom.com
SILICON VALLEY, Calif.--IPextreme, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, is adding the Freescale HCS08 8-bit microprocessor to its line of industry standard 16-bit and 32-bit microprocessors. The Freescale HCS08 is a synthesizable, state-of-the-art, high performance and low power 8-bit microprocessor that can be easily integrated into any ASIC or FPGA design. The HCS08 also provides an easy migration path to Freescale’s 32-bit ColdFire architecture. Using Freescale’s CodeWarrior integrated development environment, assembly code for the HCS08 can be retargeted to the 32-bit V1 ColdFire with just a few mouse clicks.
“We are pleased to continue to expand the portfolio of Freescale IP made available for licensing through IPextreme,” says Jeff Bock, Freescale’s Global Microcontroller Marketing Manager. “The HCS08 provides a low-cost entry point and an easy migration to our ColdFire Architecture, giving designers the flexibility they need. IPextreme’s Core Store™ enables designers to get through the IP purchase process quickly and allows them to focus on their designs.”
Freescale has shipped hundreds of millions of devices based on the HCS08 processor architecture and thousands of embedded systems are utilizing it. Since the HCS08 IP core is object code compatible with currently available Freescale 68HC08 and HCS08 devices, embedded systems currently based on these processors are easily migrated to ASICs or FPGAs, and all software is fully binary compatible. In addition, users of the HCS08 can leverage the immense ecosystem of evaluation systems, development systems, compilers and application software.
“The HCS08 is a microprocessor that has already been utilized in many market segments such as consumer, industrial, medical, automotive and low-cost networking. Providing embedded system designers with a synthesizable version allows them to integrate their designs into ASIC or FPGAs while leveraging the extensive ecosystem of hardware and software development tools and maintaining complete software compatibility,” said Rick Tomihiro, vice president of marketing for IPextreme. “As usual, IPextreme will package, license and support these synthesizable cores.”
Pricing and Availability
The Freescale HCS08 core is available for licensing now. Like all IPextreme IP, the core is offered in a complete package that includes synthesizable source code, integration test bench, and complete documentation. Encrypted versions of the core are available from the Core Store at US $10,000. Full source code versions of the HCS08 and other Core Store IP are also available for additional fees.
For additional product information, please see http://www.ip-extreme.com/IP/hcs08
To purchase the HCS08 please visit the Core Store at http://www.ip-extreme.com/corestore/
About IPextreme Inc.
IPextreme licenses famous semiconductor IP (intellectual property) and methodologies developed by large semiconductor companies to chip designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
Contacts
IPextreme Inc.Karen Crannell, 408-540-0096Karen.Crannell@ip-extreme.comor
Europe: ley PRAnnette Bley, +44 (0) 20 7482 4800annette@annettebleypr.com
North America: Cayenne Communications Linda Marchant, 919-451-0776linda.marchant@cayennecom.com
Friday, December 5, 2008
Synfora Presents Seminar to Aid SoC and FPGA Developers Design High-Performance Video Engines
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Synfora Inc., the premier provider of algorithmic synthesis tools used to design SoCs and FPGAs, will conduct a seminar on the morning of Tuesday, December 9, 2008, to show SoC and FPGA developers of video IP how to reduce design and verification time while being able to explore alternative implementations that will let them decrease silicon area and power consumption.
The seminar will be conducted by a video expert who has assisted in the architecting and implementing of several leading-edge multi-standard video engines.
The seminar will be held at the Santa Clara Techmart Meeting Center from 10:00 AM to 12:00 PM, with lunch being provided from 12:00 to 1:00.
| Who: | Synfora Inc. | ||||||
| What: | | | | | | | Technical seminar on using PICO Extreme tools to design high-performance video engines |
| When: | | | | | | | Tuesday, December 9, 2008 |
| | | | | | | | 10:00 AM – 12:00 PM |
| Where: | | | | | | | Techmart Meeting Center |
| | | | | | | | 5201 Great America Parkway |
| | | | | | | | Santa Clara CA 95054 |
Synfora’s PICO Extreme allows designers to rapidly create and verify such complex hardware sub-systems as video codecs, wireless modems and imaging pipelines from an untimed C source. This seminar will introduce the PICO verification tools and methodology and describe how they can be used to design a codec, provide other video system design examples, and include a Q&A session to help clarify any concerns or issues not otherwise covered.
Registration for the seminar is now open at http://www.synfora.com/seminar/index.html.
About Synfora Inc.
Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora's technology helps to reduce design costs, dramatically speed chip development, and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company's investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit http://www.synfora.com.
Contacts
Editorial Contact:
PR for Synfora
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
michelle.clancy@cayennecom.com
or
Joe Fowler, 408-410-2451
joe.fowler@cayennecom.com
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